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LTC2365/LTC2366 1Msps/3Msps, 12-Bit Serial Sampling ADCs in TSOT FEATURES
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DESCRIPTION
The LTC(R)2365/LTC2366 are 1Msps/3Msps, 12-bit, sampling A/D converters that draw only 2mA and 2.6mA, respectively, from a single 3V supply. These high performance devices include a high dynamic range sample-and-hold and a high speed serial interface. The full scale input is 0V to VDD or VREF . Outstanding AC performance includes 72dB SINAD and -80dB THD at sample rates of 3Msps. The serial interface provides flexible power management and allows maximum power efficiency at low throughput rates. These devices are available in tiny 6- and 8-lead TSOT-23 packages. The serial interface, tiny TSOT-23 package and extremely high sample rate-to-power ratio make the LTC2365/LTC2366 ideal for compact, low power, high speed systems. The high impedance single-ended analog input and the ability to operate with reduced spans (down to 1.4V full scale) allow direct connection to sensors and transducers in many applications, eliminating the need for gain stages.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S.
12-Bit Resolution 1Msps/3Msps Sampling Rates Low Noise: 73dB SNR Low Power Dissipation: 6mW Single Supply 2.35V to 3.6V Operation No Data Latency Sleep Mode with 0.1A Typical Supply Current Dedicated External Reference (TSOT23-8) 1V to 3.6V Digital Output Supply (TSOT23-8) SPI/MICROWIRETM Compatible Serial I/O Guaranteed Operation from -40C to 125C 6- and 8-Lead TSOT-23 Packages
APPLICATIONS
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Communication Systems Data Acquisition Systems Handheld Terminal Interface Medical Imaging Uninterrupted Power Supplies Battery Operated Systems Automotive
TYPICAL APPLICATION
12-Bit TSOT23-6/-8 ADC Family
DATA OUTPUT RATE Part Number 3Msps LTC2366 1Msps LTC2365 500ksps LTC2362 250ksps LTC2361 100ksps LTC2360
0
1MHz Sine Wave 8192 FFT Plot
VDD = 3V fSMPL = 3Msps -20 f = 994kHz IN SINAD = 72dB -40 THD = -80.3dB MAGNITUE (dB) -60 -80 -100 -120 -140 0 250
Single 3V Supply, 3Msps, 12-Bit Sampling ADC
3V 10F LTC2366 VDD VREF GND ANALOG INPUT 0V TO 3V AIN CS SDO SCK OVDD 4.7F
23656 TA01
SERIAL DATA LINK TO ASIC, PLD, MPU, DSP OR SHIFT REGISTERS DIGITAL OUTPUT SUPPLY 1V TO 3.6V
750 1000 1250 500 INPUT FREQUENCY (kHz)
1500
23656 TA01b
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LTC2365/LTC2366 ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VDD, OVDD).....................................4.0V VREF and Analog Input Voltage (Note 3).........................................-0.3V to (VDD + 0.3V) Digital Input Voltage......................-0.3V to (VDD + 0.3V) Digital Output Voltage ...................-0.3V to (VDD + 0.3V) Power Dissipation ...............................................100mW
Operating Temperature Range LTC2365C/LTC2366C ............................... 0C to 70C LTC2365I/LTC2366I.............................. -40C to 85C LTC2365H/LTC2366H (Note 13) ......... -40C to 125C Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10 sec) .................. 300C
PIN CONFIGURATION
TOP VIEW VDD 1 VREF 2 GND 3 AIN 4 8 CS 7 SCK 6 SDO 5 OVDD VDD 1 GND 2 AIN 3 TOP VIEW 6 CS 5 SDO 4 SCK
TS8 PACKAGE 8-LEAD PLASTIC TSOT-23 TJMAX = 150C, JA = 250C/W
S6 PACKAGE 6-LEAD PLASTIC TSOT-23 TJMAX = 150C, JA = 250C/W
ORDER INFORMATION
Lead Free Finish
TAPE AND REEL (MINI) LTC2366CTS8#TRMPBF LTC2366ITS8#TRMPBF LTC2366HTS8#TRMPBF LTC2366CS6#TRMPBF LTC2366IS6#TRMPBF LTC2366HS6#TRMPBF LTC2365CTS8#TRMPBF LTC2365ITS8#TRMPBF LTC2365HTS8#TRMPBF LTC2365CS6#TRMPBF LTC2365IS6#TRMPBF LTC2365HS6#TRMPBF TAPE AND REEL LTC2366CTS8#TRPBF LTC2366ITS8#TRPBF LTC2366HTS8#TRPBF LTC2366CS6#TRPBF LTC2366IS6#TRPBF LTC2366HS6#TRPBF LTC2365CTS8#TRPBF LTC2365ITS8#TRPBF LTC2365HTS8#TRPBF LTC2365CS6#TRPBF LTC2365IS6#TRPBF LTC2365HS6#TRPBF PART MARKING* LTCYZ LTCYZ LTCYZ LTCXK LTCXK LTCXK LTDCB LTDCB LTDCB LTDCC LTDCC LTDCC PACKAGE DESCRIPTION 8-lead Plastic TSOT-23 8-lead Plastic TSOT-23 8-lead Plastic TSOT-23 6-lead Plastic TSOT-23 6-lead Plastic TSOT-23 6-lead Plastic TSOT-23 8-lead Plastic TSOT-23 8-lead Plastic TSOT-23 8-lead Plastic TSOT-23 6-lead Plastic TSOT-23 6-lead Plastic TSOT-23 6-lead Plastic TSOT-23 TEMPERATURE RANGE 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C -40C to 125C
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC2365/LTC2366 CONVERTER CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Transition Noise Offset Error Gain Error Total Unadjusted Error (Note 5, 6) (Note 6) (Note 7) (Note 6) (Note 6) S6 Package (Note 6) TS8 Package (Note 6)
l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
LTC2365 CONDITIONS
l l l
LTC2366 MAX 1 1 3.5 2 3.5 4.5 MIN 12 TYP 0.25 0.25 0.34 2 1 2 3 3.5 2 3.5 4.5 MAX 1 1 UNITS Bits LSB LSB LSBRMS LSB LSB LSB LSB
MIN 12
TYP 0.25 0.25 0.34 2 1 2 3
ANALOG INPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25C. (Note 4)
PARAMETER Analog Input Voltage Analog Input Leakage Current Analog Input Capacitance Reference Input Voltage Reference Input Leakage Current Reference Input Capacitance Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter SYMBOL VIN IIN CIN VREF IREF CREF tAP tJITTER CONDITIONS S6 Package TS8 Package CS = High Between Conversions During Conversions TS8 Package TS8 Package TS8 Package
l l l l l
MIN -0.05 -0.05
TYP
MAX VDD + 0.05 VREF + 0.05 1
UNITS V V A pF pF
20 4 1.4 4 1 0.3 VDD + 0.05 1
V A pF ns ns
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25C. (Note 4)
PARAMETER Signal-to-Noise Ratio Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth LTC2365 SYMBOL SINAD SNR THD SFDR IMD CONDITIONS
l l l
LTC2366 TYP MAX UNITS 71 72 -80 82 -71.5 dB MHz MHz MHz -72 dB dB dB 68 69 -72
MIN 68 70
TYP MAX MIN 72 73 -86 87 -76 30 5 2
Signal-to-(Noise + Distortion) Ratio fIN = 1MHz fIN = 1MHz fIN = 1MHz fIN = 1MHz fIN1 = 0.97MHz, fIN2 = 1MHz for LTC2366 fIN1 = 97kHz, fIN2 = 100kHz for LTC2365 At 3dB At 0.1dB SINAD 68dB
50 8 2.5
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LTC2365/LTC2366 DIGITAL INPUTS AND DIGITAL OUTPUTS
SYMBOL VIH VIL IIH IIL CIN VOH VOL IOZ COZ ISOURCE ISINK PARAMETER High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage Hi-Z Output Capacitance Output Source Current Output Sink Current VDD = 2.35V to 3.6V, ISOURCE = 200A VDD = 2.35V to 3.6V, ISINK = 200A CS = VDD CS = VDD VOUT = 0V VOUT = VDD
l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS 2.7V < VDD 3.6V 2.35V VDD 2.7V 2.7V < VDD 3.6V 2.35V VDD 2.7V VIN = VDD VIN = 0V
l l l l l l
MIN 2 1.7
TYP
MAX
UNITS V V
0.8 0.7 2.5 -2.5 2 VDD -0.2 0.2 3 4 -10 10
V V A A pF V V A pF mA mA
POWER REQUIREMENT
SYMBOL VDD OVDD IDD PARAMETER Supply Voltage Digital Output Supply Voltage Supply Current, Static Mode Operational Mode, LTC2366 Operational Mode, LTC2365 Sleep Mode Sleep Mode Power Dissipation, Static Mode Operational Mode, LTC2366 Operational Mode, LTC2365 Sleep Mode Sleep Mode CS = 0V, SCK = 0V or VDD fSMPL = 3Msps fSMPL = 1Msps -40C to +85C +85C to +125C CS = 0V, SCK = 0V or VDD fSMPL = 3Msps fSMPL = 1Msps -40C to +85C +85C to +125C CONDITIONS
l l l l l l l l l l
MIN 2.35 1
TYP 3.0 1 2.6 2 0.1
MAX 3.6 3.6 4 3.5 2 5 3.6 14.4 12.6 7.2 18
UNITS V V mA mA mA A A mW mW mW W W
PD
7.8 6 0.3
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LTC2365/LTC2366
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
LTC2365 SYMBOL fSMPL(MAX) fSCK tSCK tTHROUGHPUT tACQ tCONV tQUIET t1 t2 t3 t4 t5 t6 t7 t8 t9 tPOWER-UP PARAMETER Maximum Sampling Frequency Shift Clock Frequency Shift Clock Period Minimum Throughput Time, tACQ + tCONV Acquisition Time Conversion Time SDO Hi-Z State to CS SCK Setup Time After CS SDO Enabled Time After CS SDO Data Valid Access Time After SCK SCK Low Time SCK High Time SDO Data Valid Hold Time After SCK SDO Into Hi-Z State Time After SCK SDO Into Hi-Z State Time After CS Power-up Time from Sleep Mode (Notes 8, 9, 11) (Notes 9, 12) (Notes 9, 12) See Sleep Mode section (Notes 8, 9) (Notes 8) (Notes 9, 11, 12) (Notes 8, 9, 11) Minimum Positive or Negative CS Pulse Width (Notes 8) CONDITIONS (Notes 8, 9) (Notes 8, 9, 10)
l l l l l l l l l l l l l l l l l
TIMING CHARACTERISTICS
LTC2366 MAX 16 2000 1000 MIN 3 0.5 20.8 56 277 4 4 2000 4 15 6 2000 4 15 40% 40% 5 30 4.2 1000 5 14 4.2 333 48 2000 333 TYP MAX UNITS MHz MHz ns ns ns ns ns ns ns ns ns tSCK tSCK ns ns ns ns
MIN 1 0.5 62.5 181.5 818.5 4 4 6
TYP
40% 40% 5 5
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: When this pin, AIN, is taken below GND or above VDD, it will be clamped by internal diodes. These products can handle input currents greater than 100mA below GND or above VDD without latchup. Note 4: VDD = OVDD = VREF = 2.35V to 3.6V, fSMPL = fSMPL(MAX) and fSCK = fSCK(MAX) unless otherwise specified. Note 5: Integral linearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
Note 6: Linearity, offset and gain specifications apply for a single-ended AIN input with respect to GND. Note 7: Typical RMS noise at code transitions. Note 8: Guaranteed by characterization. All input signals are specified with tr = tf = 2ns (10% to 90% of VDD) and timed from a voltage level of 1.6V. Note 9: All timing specifications given are with a 10pF capacitance load. With a capacitance load greater than this value, a digital buffer or latch must be used. Note 10: Minimum fSCK at which specifications are guaranteed. Note 11: The time required for the output to cross the VIH or VIL voltage. Note 12: Guaranteed by design, not subject to test. Note 13: High temperatures degrade operating lifetimes. Operating lifetime is derated at temperatures greater than 105C.
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LTC2365/LTC2366 TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity vs Output Code
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 3072 OUTPUT CODE 4096
23656 G01
TA = 25C, VDD = OVDD = VREF (LTC2365, Note 4) Integral and Differential Nonlinearity vs Supply Voltage
1.0 0.8 0.6 INL AND DNL (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 MIN DNL MIN INL MAX DNL MAX INL
Differential Nonlinearity vs Output Code
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 3072 OUTPUT CODE 4096
23656 G02
VDD = 3V
VDD = 3V
-1.0 2.1
2.4
3.0 3.3 2.7 SUPPLY VOLTAGE (V)
3.6
23656 G03
Histogram for 16384 Conversions
10000 VDD = 3V 73.5
SNR vs Input Frequency
73.2 VDD = 3.6V
SINAD vs Input Frequency
VDD = 3.6V 73.0 72.8 VDD = 3V
8000
73.3
SNR (dB)
COUNT
6000
73.1
VDD = 3V
SINAD (dB)
72.6 72.4 VDD = 2.35V
4000
72.9 VDD = 2.35V
2000
72.7
72.2 72.0 100 INPUT FREQUENCY (kHz)
23656 G05 23656 G06
0
2045
2046
2047 2048 CODE
2049
2050
23656 G04
72.5 100 INPUT FREQUENCY (kHz)
1000
1000
THD vs Input Frequency
-81 -82 -83 THD (dB) -84 -85 -86 -87 -88 100 INPUT FREQUENCY (kHz)
23656 G07
THD vs Input Resistance
-78 VDD = 3V fSMPL = 1Msps fIN = 1MHz MAGNITUDE (dB) 0
461kHz Sine Wave 8192 FFT Plot
VDD = 3V fSMPL = 1Msps -20 f = 461kHz IN SINAD = 72.8dB -40 THD = -86.1dB -60 -80 -100
RIN = 10 fSMPL = 1Msps
-79
VDD = 3V VDD = 2.35V VDD = 3.6V
THD (dB)
-80
-81
-82 -120 -83 -140 0 50 25 75 INPUT RESISTANCE () 100
23656 G08
1000
0
100
200 300 400 INPUT FREQUENCY (kHz)
500
23656 G09
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LTC2365/LTC2366 TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity vs Output Code
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 3072 OUTPUT CODE 4096
23656 G10
TA = 25C, VDD = OVDD = VREF (LTC2366, Note 4) Integral and Differential Nonlinearity vs Supply Voltage
1.0 0.8 0.6 INL AND DNL (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 MIN DNL MIN INL MAX DNL MAX INL
Differential Nonlinearity vs Output Code
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 3072 OUTPUT CODE 4096
23656 G11
VDD = 3V
VDD = 3V
-1.0 2.1
2.4
3.0 3.3 2.7 SUPPLY VOLTAGE (V)
3.6
23656 G12
Histogram for 16384 Conversions
10000 VDD = 3V 73.2
SNR vs Input Frequency
73.0 VDD = 3.6V
SINAD vs Input Frequency
VDD = 3.6V 72.5 72.0 VDD = 2.35V VDD = 3V
8000
73.0 SINAD (dB)
SNR (dB)
COUNT
6000
72.8
VDD = 3V
71.5 71.0
4000
72.6 VDD = 2.35V
2000
72.4
70.5 70.0 100 INPUT FREQUENCY (kHz)
23656 G14 23656 G15
0
2045
2046
2047 2048 CODE
2049
2050
23656 G13
72.2 100 INPUT FREQUENCY (kHz)
1000 1500
1000 1500
THD vs Input Frequency
-72 -74 -76 THD (dB) THD (dB) -78 -80 VDD = 3.6V -82 -84 VDD = 3V -86 VDD = 2.35V -88 100 INPUT FREQUENCY (kHz)
23656 G16
THD vs Input Resistance
-64 -66 -68 -70 -72 -74 -76 -78 0 25 75 INPUT RESISTANCE () 50 100
23656 G17
1MHz Sine Wave 8192 FFT Plot
VDD = 3V fSMPL = 3Msps -20 f = 994kHz IN SINAD = 72dB -40 THD = -80.3dB MAGNITUE (dB) -60 -80 -100 -120 -140 0 250 0
RIN = 10 fSMPL = 3Msps
VDD = 3V fSMPL = 3Msps fIN = 1.5MHz
1000 1500
750 1000 1250 500 INPUT FREQUENCY (kHz)
1500
23656 G18
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LTC2365/LTC2366 TYPICAL PERFORMANCE CHARACTERISTICS
Reference Current vs SCK Frequency (TS8 Package)
250 16 SCKS PER CONVERSION NONLINEARITY ERROR (LSB) 1.0 0.8 2.5 2.0 IDD (mA) 1.5 VDD = 2.35V 1.0 0.5 0 0 10 20 30 40 SCK FREQUENCY (MHz) 50
23656 G19
TA = 25C, VDD = OVDD = VREF (LTC2365/LTC2366, Note 4) Integral and Differential Nonlinearity vs Reference Voltage (TS8 Package)
LTC2365, VDD = 3.6V
Supply Current vs SCK Frequency
3.0
REFERENCE CURRENT (A)
VDD = 3.6V
200
0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0.6
MAX DNL
150 VDD = 3V 100 VDD = 3.6V
MAX INL
VDD = 3V
MIN DNL
MIN INL
50 VDD = 2.35V 0 0 5 10 15 20 25 30 35 40 45 50 SCK FREQUENCY (MHz)
23656 G20
1.2 2.4 3.0 1.8 REFERENCE VOLTAGE (V)
3.6
23656 G21
Integral and Differential Nonlinearity vs Reference Voltage (TS8 Package)
1.0 0.8 NONLINEARITY ERROR (LSB) 0.6 MAGNITUDE (dB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0.6 -10 1.2 2.4 3.0 1.8 REFERENCE VOLTAGE (V) 3.6
23656 G22
Input Power Bandwidth
2 0 LTC2366 -2 -4 LTC2365 -6 -8 VDD = 3V
LTC2366, VDD = 3.6V
MAX DNL MAX INL
MIN DNL
MIN INL
1
10 INPUT FREQUENCY (MHz)
100
23656 G23
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LTC2365/LTC2366 PIN FUNCTIONS
LTC2365/LTC2366 (S6 Package) VDD (Pin 1): Positive Supply. The VDD range is 2.35V to 3.6V. VDD also defines the input span of the ADC, 0V to VDD. Bypass to GND and to a solid ground plane with a 10F ceramic capacitor (or 10F tantalum in parallel with 0.1F ceramic). GND (Pin 2): Ground. The GND pin must be tied directly to a solid ground plane. AIN (Pin 3): Analog Input. AIN is a single-ended input with respect to GND with a range from 0V to VDD. SCK (Pin 4): Shift Clock Input. The SCK serial clock advances the conversion process. SDO data transitions on the falling edge of SCK. SDO (Pin 5): Three-state Serial Data Output. The A/D conversion result is shifted out on SDO as a serial data stream with MSB first. The data stream consists of two leading zeros followed by 12 bits of conversion data and two trailing zeros. CS (Pin 6): Chip Select Input. This active low signal starts a conversion on the falling edge and frames the serial data transfer. LTC2365/LTC2366 (TS8 Package) VDD (Pin 1): Positive Supply. The VDD range is 2.35V to 3.6V. Bypass to GND and to a solid ground plane with a 10F ceramic capacitor (or 10F tantalum in parallel with 0.1F ceramic). VREF (Pin 2): Reference Input. VREF defines the input span of the ADC, 0V to VREF and the VREF range is 1.4V to VDD. Bypass to GND and to a solid ground plane with a 4.7F ceramic capacitor (or 4.7F tantalum in parallel with 0.1F ceramic). GND (Pin 3): Ground. The GND pin must be tied directly to a solid ground plane. AIN (Pin 4): Analog Input. AIN is a single-ended input with respect to GND with a range from 0V to VREF. OVDD (Pin 5): Output Driver Supply for SDO. The OVDD range is 1V to 3.6V. Bypass to GND and to a solid ground plane with a 4.7F ceramic capacitor (or 4.7F tantalum in parallel with 0.1F ceramic). SDO (Pin 6): Three-state Serial Data Output. The A/D conversion result is shifted out on SDO as a serial data stream with MSB first. The data stream consists of two leading zeros followed by 12 bits of conversion data and two trailing zeros. SCK (Pin 7): Shift Clock Input. The SCK serial clock advances the conversion process. SDO data transitions on the falling edge of SCK. CS (Pin 8): Chip Select Input. This active low signal starts a conversion on the falling edge and frames the serial data transfer.
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LTC2365/LTC2366 BLOCK DIAGRAM
10F 4.7F VDD 1 ANALOG INPUT RANGE OV TO VREF AIN 4 5
+
+
OVDD
+
S&H 12-BIT ADC
-
VREF
THREESTATE SERIAL OUTPUT PORT
6
SDO
+
4.7F GND
2 TIMING LOGIC 3 TS8 PACKAGE
7
SCK
8
CS
23656 BD
TIMING DIAGRAMS
t8 SCK 1.6V
SDO
Hi-Z
23656 TD01
Figure 1. SDO Into Hi-Z State After SCK Falling Edge
t7 SCK 1.6V
SDO
VIH VIL
23656 TD02
Figure 2. SDO Data Valid Hold Time After SCK Falling Edge
t4 SCK 1.6V
SDO
VOH VOL
23656 TD03
Figure 3. SDO Data Valid Access Time After SCK Falling Edge
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LTC2365/LTC2366 APPLICATIONS INFORMATION
DC PERFORMANCE The noise of an ADC can be evaluated in two ways: signalto-noise ratio (SNR) in the frequency domain and histogram in the time domain. The LTC2365/LTC2366 excel in both. Figures 5 and 6 demonstrate that the LTC2365/LTC2366 have an SNR of over 72dB. The noise in the time domain histogram is the transition noise associated with a 12-bit resolution ADC which can be measured with a fixed DC signal applied to the input of the ADC. The resulting output codes are collected over a large number of conversions. The shape of the distribution of codes will give an indication of the magnitude of the transition noise. In Figure 4, the distribution of output codes is shown for a DC input that has been digitized 16384 times. The distribution is Gaussian and the RMS code transition is about 0.34LSB. This corresponds to a noise level of 72.7dB relative to a full scale of 3V. DYNAMIC PERFORMANCE The LTC2365/LTC2366 have excellent high speed sampling capability. Fast fourier transform (FFT) test techniques are used to test the ADC's frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC's spectral content can be examined for frequencies outside the fundamental. Figures 5 and 6 show typical LTC2365 and LTC2366 FFT plots respectively.
VDD = 3V fSMPL = 1Msps -20 fIN = 461kHz SINAD = 72.8dB -40 THD = -86.1dB -60 -80 -100 -120 -140 0 100 200 300 400 INPUT FREQUENCY (kHz) 500
23656 F05
0
MAGNITUDE (dB)
Figure 5. LTC2365 FFT Plot
10000 VDD = 3V VDD = 3V fSMPL = 3Msps -20 f = 994kHz IN SINAD = 72dB -40 THD = -80.3dB MAGNITUE (dB) -60 -80 -100 2000 -120 -140 2045 2046 2047 2048 CODE 2049 2050
23656 F04
0
8000
COUNT
6000
4000
0
0
250
750 1000 1250 500 INPUT FREQUENCY (kHz)
1500
23656 F06
Figure 4. Histogram for 16384 Conversions
Figure 6. LTC2366 FFT Plot
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LTC2365/LTC2366 APPLICATIONS INFORMATION
Signal-to-Noise plus Distortion Ratio The signal-to-noise plus distortion ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 6 shows a typical FFT with a 3MHz sampling rate and a 1MHz input. The dynamic performance is excellent for input frequencies up to and beyond the Nyquist frequency of 1.5MHz. Effective Number of Bits The effective number of bits (ENOB) is a measurement of the resolution of an ADC and is directly related to SINAD by the equation: ENOB = (SINAD - 1.76)/6.02 where ENOB is the effective number of bits of resolution and SINAD is expressed in dB. At the maximum
73.0 VDD = 3.6V 72.5 72.0 SINAD (dB) 71.5 71.0 70.5 70.0 100 INPUT FREQUENCY (kHz)
23656 F07
sampling rate of 3MHz, the LTC2366 maintains ENOB above 11 bits up to the Nyquist input frequency of 1.5MHz (refer to Figure 7). Total Harmonic Distortion The total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. THD versus Input Frequency is shown in Figure 8. The LTC2366 has excellent distortion performance up to the Nyquist frequency and beyond.
-72 -74 -76 RIN = 10
THD = 20log
V2 2 + V3 2 + V4 2 + ...Vn 2
11.83
VDD = 2.35V VDD = 3V
11.67 THD (dB) ENOB 11.50 11.34 1000 1500
-78 -80 VDD = 3.6V -82 -84 -86 VDD = 2.35V -88 100 INPUT FREQUENCY (kHz)
23656 F08
VDD = 3V
1000 1500
Figure 7. LTC2366 ENOB and SINAD vs Input Frequency
Figure 8. LTC2366 Distortion vs Input Frequency
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LTC2365/LTC2366 APPLICATIONS INFORMATION
Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermoduation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfanfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula: Amplitude at (fa fb ) IMD(fa fb ) = 20log Amplitude at fa The LTC2365/LTC2366 have good IMD as shown in Figure 9a and Figure 9b respectively.
VDD = 3V = 1Msps f -20 fSMPL b = 396kHz fb = 424kHz -40 IMD = -73.5dB MAGNITUE (dB) -60 -80 -100 -120 -140 0 50 100 150 200 250 300 350 400 450 500 INPUT FREQUENCY (kHz)
23656 F09a
Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal. Full-Power and Full-Linear Bandwidth The full-power bandwidth is that input frequency at which the amplitude of reconstructed fundamental is reduced by 3dB for full-scale input signal. The full-linear bandwidth is the input frequency at which the SINAD has dropped to 68dB (11 effective bits). The LTC2365/LTC2366 have been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter's Nyquist Frequency. The noise floor stays very low at high frequencies; SINAD becomes dominated by distortion at frequencies far beyond Nyquist.
0
MAGNITUDE (dB)
VDD = 3V fSMPL = 3Msps -20 f = 935kHz a fb = 1.045kHz -40 IMD = -71.5dB -60 -80 -100 -120 -140 0 250
0
750 1000 1250 500 INPUT FREQUENCY (kHz)
1500
23656 F09b
Figure 9a. LTC2365 Intermodulation Distortion Plot
Figure 9b. LTC2366 Intermodulation Distortion Plot
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LTC2365/LTC2366 APPLICATIONS INFORMATION
OVERVIEW The LTC2365/LTC2366 use a successive approximation algorithm and internal sample-and-hold circuit to convert an analog signal to a 12-bit serial output. Both devices operate from a single 2.35V to 3.6V supply. The LTC2366 samples at a rate of 3Msps with a 48MHz clock while the LTC2365 samples at a rate of 1Msps with a 16MHz clock. The LTC2365/LTC2366 contain a 12-bit, switched-capacitor ADC, a sample-and-hold, and a serial interface (see Block Diagram) and are available in tiny 6- and 8-lead TSOT-23 packages. The devices provide sleep mode control through the serial interface to save power during inactive periods (see the SLEEP MODE section). The S6 package of the LTC2365/LTC2366 uses VDD as the reference and has an analog input range of 0V to VDD. The ADC samples the analog input with respect to GND and outputs the result through the serial interface. The TS8 package provides two additional pins: a reference input pin, VREF, and an output supply pin, OVDD. The ADC can operate with reduced spans down to 1.4V and achieve 342V resolution. OVDD controls the output swing of the digital output pin, SDO, and allows the device to communicate with 1.8V, 2.5V or 3V digital systems. SERIAL INTERFACE The LTC2365/LTC2366 communicate with microcontrollers, DSPs and other external circuitry via a 3-wire interface. Figure 10 shows the serial interface timing diagram, while Figures 11 and 12 detail the timing diagrams of conversion cycles in 14 and 16 SCK cycles respectively. Data Transfer A falling CS edge starts a conversion and frames the serial data transfer. SCK provides the conversion clock and controls the data transfer during the conversion. CS going low clocks out the first leading zero and subsequent SCK falling edges clock out the remaining data, beginning with the second leading zero. (Therefore, the first SCK falling edge captures the first leading zero and clocks out the second leading zero). The timing diagram in Figure 12 shows that the final bit in the data transfer is valid on the 16th falling edge, since it is clocked out on the previous 15th falling edge. In applications with a slower SCK, it is possible to capture data on each SCK rising edge. In such cases, the first falling edge of SCK clocks out the second leading zero and can be captured on the first rising edge. However, the first leading zero clocked out when CS goes low is missed as shown in Figures 11 and 12. In Figure 12, the 15th falling edge of SCK clocks out the last bit and can be captured on the 15th rising SCK edge. If CS goes low while SCK is low, then CS clocks out the first leading zero and can be captured on the SCK rising edge. The next SCK falling edge clocks out the second leading zero and can be captured on the following rising edge as shown in in Figure 10.
t1 CS tCONV t2 SCK t3 SDO ZERO ZERO B11 (MSB) 13tSCK tTHROUGHPUT
23656 F10
t6 1 2 3 4 t4 B10 B9 5 t7 B1 B0 13 14 t5 ZERO ZERO tACQ 15 16 t8 tQUIET Hi-Z STATE
Figure 10. LTC2365/LTC2366 Serial Interface Timing Diagram
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LTC2365/LTC2366 APPLICATIONS INFORMATION
Achieving 3Msps Sample Rate with LTC2366 CS going low places the sample-and-hold into hold mode and starts a conversion. The LTC2365/LTC2366 require at least 14 SCK cycles to finish the conversion. The conversion terminates after the 13th falling SCK edge, which clocks out B0. The 14th falling SCK edge places the sample-and-hold back into sample mode. Ignoring the last two trailing zeros, the user can bring CS high after the 14th falling SCK edge. The user can also keep the last two trailing zeros by bringing CS high right after the 16th falling SCK. In both cases, a sample rate of 3Msps can be achieved by using a 48MHz SCK clock on the LTC2366, where tTHROUGHPUT is 333ns. Serial Data Output (SDO) The SDO output remains in the high impedance state while CS is high. The falling edge of CS starts the conversion and enables SDO. The A/D conversion result is shifted out on the SDO pin as a serial data stream with the MSB first. The data stream consists of two leading zeros followed by 12 bits of conversion data and two trailing zeros. The SDO output returns to the high impedance state at the 16th falling edge of SCK or sooner by bringing CS high before the 16th falling edge of SCK. The output swing on the SDO pin is controlled by the VDD pin voltage in the S6 package and by the OVDD pin voltage in the TS8 package.
t1 CS tCONV t2 SCK 1 t3 SDO Z ZERO B11 (MSB) tTHROUGHPUT
23656 F11
tACQ t6 4 t4 5 t7 B1 13 t5 B0 14 t9 tQUIET Hi-Z STATE
2
3
B10
B9
Figure 11. LTC2365/LTC2366 Serial Interface Timing Diagram for 14 SCK Cycles
t1 CS tCONV t2 SCK 1 t3 SDO Z ZERO B11 (MSB) tTHROUGHPUT
23656 F12
tACQ t6 4 t4 5 t7 B1 B0 13 14 t5 ZERO ZERO Hi-Z STATE 15 16 t8 OR t9 tQUIET
2
3
B10
B9
Figure 12. LTC2365/LTC2366 Serial Interface Timing Diagram for 16 SCK Cycles
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LTC2365/LTC2366 APPLICATIONS INFORMATION
SLEEP MODE The LTC2365/LTC2366 provide a sleep mode to conserve power during inactive periods. Upon power-up, holding CS high initializes the ADC to sleep mode. In sleep mode, all bias circuitry is shut down and only leakage currents remain (0.1A typ). Entering Sleep Mode The ADC achieves the fastest sampling rate in operational mode (full power-up). The device can also be put into sleep mode for power savings during inactive periods. To force the LTC2365/LTC2366 into sleep mode, the user can interrupt the conversion process by bringing CS high between the 2nd and 10th falling edges of SCK (see Figures 13 and 14). If CS is brought high after the 10th falling edge and before the 16th falling edge, the device remains powered up, but the conversion is terminated and SDO returns to the high impedance state.
CS 1 SCK SDO 2 10 12 14 16
VALID DATA
23656 F13
Figure 13. LTC2365/LTC2366 Operational Mode
CS
1 SCK
2
10
12
14
16
SDO
Hi-Z STATE
23656 F14
Figure 14. LTC2365/LTC2366 Entering Sleep Mode
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LTC2365/LTC2366 APPLICATIONS INFORMATION
Exiting Sleep Mode and Power-Up Time To exit sleep mode, pull CS low and perform a dummy conversion. The LTC2365/LTC2366 device power up completely after the 16th falling edge of SCK. After powering up, the ADC can continuously acquire an input signal and perform conversions as described in the SERIAL INTERFACE section (see Figure 15). The wake-up time is 333ns for the LTC2366 with a 48MHz SCK and 1s for the LTC2365 with a 16MHz SCK. The sample-and-hold is in hold mode while the device is in sleep mode. The ADC returns to sample mode after the 1st falling edge of SCK during power-up (see Figure 15).
THE DEVICE BEGINS TO POWER UP THE DEVICE BEGINS TO ACQUIRE INPUT tPOWER-UP THE DEVICE IS FULLY POWERED UP AND READY TO PERFORM CONVERSION
POWER VERSUS SAMPLING RATE Figure 16 shows the power consumption of the LTC2365/ LTC2366 in operational mode. By taking the ADC into sleep mode when not performing a conversion, the average power consumption of the ADC decreases as the sampling rate decreases. Figure 17 shows the power consumption versus sampling rate with the device in sleep mode when not performing a conversion.
CS 1 SCK SDO 2 10 12 14 16 12 10 12 14 16
INVALID DATA
VALID DATA
23656 F15
Figure 15. LTC2365/LTC2366 Exiting Sleep Mode
7.5 7.0 6.5 POWER (mW) POWER (mW) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 0 500 1000 1500 2000 SAMPLE RATE (ksps) 2500 3000 VDD = 3V fSCK = VARIABLE 16 SCKS PER CONVERSION 8 VDD = 3V 7 fSCK = 48MHz 6 5 4 3 2 1 0 0 500 250 750 SAMPLE RATE (ksps) 1000
23656 F17
23656 F16
Figure 16. Power Consumption vs Sample Rate while the Device Remains Powered Up Continuously
Figure 17. Power Consumption vs Sample Rate while the Device Enters Sleep Mode when not Performing Conversions
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LTC2365/LTC2366 APPLICATIONS INFORMATION
SINGLE-ENDED ANALOG INPUT Driving the Analog Input The analog input of the LTC2365/LTC2366 is easy to drive. The input draws only one small current spike while charging the sample-and-hold capacitor at the end of conversion. During the conversion, the analog input draws only a small leakage current. If the source impedance of the driving circuit is low, then the input of the LTC2365/LT2366 can be driven directly. As source impedance increases, so will acquisition time. For minimum acquisition time with high source impedance, a buffer amplifier should be used. The main requirement is that the amplifier driving the analog input must settle after the small current spike before the next conversion starts (settling time must be less than 56ns for full throughput rate). While choosing an input amplifier, also keep in mind the amount of noise and harmonic distortion the amplifier contributes. Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (<100) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a gain of 1 and has a unitygain bandwidth of 50MHz, then the output impedance at 50MHz must be less than 100. The second requirement is that the closed-loop bandwidth must be greater than 40MHz to ensure adequate small signal settling for full throughput rate. If slower op amps are used, more time for settling can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC2365/LTC2366 will depend on the application. Generally, applications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC2365/LTC2366. (More detailed information is available on the Linear Technology website at www.linear.com.)
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LTC2365/LTC2366 APPLICATIONS INFORMATION
LTC1566-1: Low Noise 2.3MHz Continuous Time LowPass Filter. LT1630: Dual 30MHz Rail-to-Rail Voltage Feedback Amplifier. 2.7V to 15V supplies. Very high AVOL, 500V offset and 520ns settling to 0.5LSB for a 4V swing. THD and noise are -93dB to 40kHz and below 1LSB to 320kHz (AV = 1, 2VP-P into 1k, VS = 5V), making the part excellent for AC applications (to 1/3 Nyquist) where rail-to-rail performance is desired. Quad version is available as LT1631. LT1632: Dual 45MHz Rail-to-Rail Voltage Feedback Amplifier. 2.7V to 15V supplies. Very high AVOL, 1.5mV offset and 400ns settling to 0.5LSB for a 4V swing. It is suitable for applications with a single 5V supply. THD and noise are -93dB to 40kHz and below 1LSB to 800kHz (AV = 1, 2VP-P into 1k, VS = 5V), making the part excellent for AC applications where rail-to-rail performance is desired. Quad version is available as LT1633. LT1813: Dual 100MHz 750V/s 3mA Voltage Feedback Amplifier. 5V to 5V supplies. Distortion is -86dB to 100kHz and -77dB to 1MHz with 5V supplies (2VP-P into 500). Excellent part for fast AC applications with 5V supplies. LT1801: 180MHz GBWP -75dBc at 500kHz, 2mA/Ampli, fier, 8.5nV/Hz. LT1806/LT1807: 325MHz GBWP -80dBc Distortion at , 5MHz, Unity-Gain Stable, R-R In and Out, 10mA/Amplifier, 3.5nV/Hz. LT1810: 180MHz GBWP -90dBc Distortion at 5MHz, , Unity-Gain Stable, R-R In and Out, 15mA/Amplifier, 16nV/Hz. LT1818/LT1819: 400MHz, 2500V/s, 9mA, Single/Dual Voltage Mode Operational Amplifier. LT6200: 165MHz GBWP -85dBc Distortion at 1MHz, , Unity-Gain Stable, R-R In and Out, 15mA/Amplifier, 0.95nV/Hz. LT6203: 100MHz GBWP -80dBc Distortion at 1MHz, , Unity-Gain Stable, R-R In and Out, 3mA/Amplifier, 1.9nVHz. Input Filtering and Source Impedance The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC2365/LTC2366 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 50MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. For example, Figure 18 shows a 47pF capacitor from AIN to ground and a 51 source resistor to limit the input bandwidth to 47MHz. The 47pF capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling-glitch sensitive circuitry. High quality capacitors and resistors should be used since these components can add distortion. NPO and silvermica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. When high amplitude unwanted signals are close in frequency to the desired signal frequency, a multiple pole filter is required. High external source resistance, combined with the 20pF of input capacitance, will reduce the rated 50MHz bandwidth and increase acquisition time beyond 56ns.
LTC2366 1 10F 2 47pF 51 GND VDD CS SD0 SCK 6 5 4
3A IN
23656 F18
Figure 18. RC Input Filter
LinearView is a trademark of Linear Technology Corpration
23656f
19
LTC2365/LTC2366 APPLICATIONS INFORMATION
Reference Input On the TS8 package of the LTC2365/LTC2366, the voltage on the VREF pin defines the full-scale range of the ADC. The reference voltage can range from VDD down to 1.4V. Input Range The analog input of the LTC2365/LTC2366 is driven singleended with respect to GND from a single supply. The input may swing up to VDD for the S6 package and to VREF for the TS8 package. The 0V to 2.5V range is also ideally suited for single-ended input use with VDD or VREF = 2.5V for single supply applications. If the difference between the AIN input and GND exceeds VDD for the S6 package or VREF for the TS8 package, the output code will stay fixed at all ones, and if this difference goes below 0V, the output code will stay fixed at all zeros. Figure 19 shows the ideal input/output characteristics for the LTC2365/LTC2366. The code transitions occur midway between successive integer LSB values (i.e. 0.5LSB, 1.5LSB, 2.5LSB, ..., FS -1.5LSB). The output code is straight binary with 1LSB = VDD/4096 for the S6 package and 1LSB = VREF /4096 for the TS8 package. BOARD LAYOUT AND BYPASSING Wire wrap boards are not recommended for high resolution and/or high speed A/D converters. To obtain the best performance from the LTC2365/LTC2366, a printed circuit board with ground plane is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. The analog input should be screened by the ground plane.
111...111 111...110 UNIPOLAR OUTPUT CODE 000...001 000...000 0 1LSB INPUT VOLTAGE (V)
23656 F19
FS - 1LSB
Figure 19. LTC2365/LTC2366 Transfer Characteristics
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LTC2365/LTC2366 APPLICATIONS INFORMATION
High quality tantalum and ceramic bypass capacitors should be used at the VDD and VREF pins as shown in the Typical Application circuit on the first page of this data sheet. For optimum performance, a 10F surface mount AVX capacitor with a 0.1F ceramic is recommended for the VDD pin and a 4.7F surface mount AVX capacitor with a 0.1F ceramic is recommended for the VREF and OVDD pins. Alternatively, 4.7F and 10F ceramic chip capacitors such as Murata GRM235Y5V106Z016 may be used. The capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. Figure 20 shows the recommended system ground connections. All analog circuitry grounds should be terminated at the LTC2365/LTC2366. The ground return from the LTC2365/LTC2366 to the power supply should be low impedance for noise free operation. Digital circuitry grounds must be connected to the digital supply common. In applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a Wait state during conversion or by using three-state buffers to isolate the ADC data bus.
+
CV DD
10F
PIN 1 CAIN
VDD GND AIN
CS SDO SCK
VIAS TO GROUND PLANE
23656 F20
Figure 20. Power Supply Ground Practice
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LTC2365/LTC2366 PACKAGE DESCRIPTION
S6 Package 6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
0.62 MAX 0.95 REF 2.90 BSC (NOTE 4)
1.22 REF
3.85 MAX 2.62 REF
1.4 MIN
2.80 BSC
1.50 - 1.75 (NOTE 4) PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR
0.95 BSC
0.30 - 0.45 6 PLCS (NOTE 3)
0.80 - 0.90 0.20 BSC DATUM `A' 1.00 MAX 0.01 - 0.10
0.30 - 0.50 REF
NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING
0.09 - 0.20 (NOTE 3)
1.90 BSC
S6 TSOT-23 0302 REV B
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193
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LTC2365/LTC2366 PACKAGE DESCRIPTION
TS8 Package 8-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1637)
0.52 MAX 0.65 REF 2.90 BSC (NOTE 4)
1.22 REF
3.85 MAX 2.62 REF
1.4 MIN
2.80 BSC
1.50 - 1.75 (NOTE 4) PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR
0.65 BSC
0.22 - 0.36 8 PLCS (NOTE 3)
0.80 - 0.90 0.20 BSC DATUM `A' 1.00 MAX 0.01 - 0.10
0.30 - 0.50 REF
NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING
0.09 - 0.20 (NOTE 3)
1.95 BSC
TS8 TSOT-23 0802
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC2365/LTC2366 TYPICAL APPLICATION
Low-Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level Shifting Circuit and Re-Timing Flip-Flop
VCC 1k NC7SVU04P5X MASTER CLOCK VCC 50 1k 0.1F
D
PRE
Q Q CONV
CLR NL17SZ74 CONVERT ENABLE CONV LTC2366 SCK NC7SVU04P5X SDO 100
CONTROL LOGIC (FPGA, CPLD, DSP ETC.) ,
2365/2366 TA02
RELATED PARTS
PART NUMBER ADCs LTC1402 LTC1403/LTC1403A LTC1407/LTC1407A LTC1860 LTC1860L LTC1861 LTC1861L LTC1863 LTC1863L LTC1864/LTC1865 LTC1867 LTC1867L LTC2355/LTC2356 DACs LTC1592 LTC2630 References LT1460-2.5 LT1461-2.5 LT1790-2.5 LT6660 Micropower Series Voltage Reference Precision Voltage Reference Micropower Series Reference in SOT-23 Ultra-Tiny Micropower Series Reference 0.1% Initial Accuracy, 10ppm Drift 0.05% Initial Accuracy, 3ppm Drift 0.05% Initial Accuracy, 10ppm Drift 2mm x 2mm DFN Package, 0.2% Initial Accuracy, 10ppm Drift
23656f LT 0408 * PRINTED IN USA
DESCRIPTION 12-Bit, 2.2Msps Serial ADC 12-/14-Bit, 2.8Msps Serial Sampling ADC 12-Bit, 250ksps Serial ADC 12-Bit, 150ksps Serial ADC 12-Bit, 250ksps Serial ADC 12-Bit, 150ksps Serial ADC 12-Bit, 200ksps Serial ADC 8-Channel ADC 12-Bit, 250ksps Serial ADC 8-Channel ADC 16-Bit, 250ksps Serial ADC 16-Bit, 200ksps Serial ADC 8-Channel ADC 16-Bit, 175ksps Serial ADC 8-Channel ADC 12-/14-Bit, 3.5Msps Serial ADC
COMMENTS 5V or 5V Supply, 4.096V or 2.5V Span 3V, Differential Input, 12mW, MSOP Package 5V Supply, 1-Channel, 4.3mW, MSOP-8 Package 3V Supply, 1-Channel, 1.3mW, MSOP-8 Package 5V Supply, 2-Channel, 4.3mW, MSOP-8 Package 3V Supply, 2-Channel, 1.3mW, MSOP-8 Package 5V Supply, 6.5mW, SSOP-16 Package, Pin Compatible to LTC1863L, LTC1867 5V Supply, 2.2mW, SSOP-16 Package, Pin Compatible to LTC1863, LTC1867L 5V Supply, 1 and 2 Channel, 4.3mW, MSOP Package 5V Supply, 6.5mW, SSOP-16 Package, Pin Compatible to LTC1863, LTC1867L 3V Supply, 2.2mW, SSOP-16 Package, Pin Compatible to LTC1863L, LTC1867 3.3V Supply, Differential Input, 18mW, MSOP Package 3V Supply, Pin- and Software-Compatible to LTC2365/LTC2366 1LSB INL/DNL, Software Selectable Spans 87dB SFDR, 20ns Settling Time SC70 6-Pin Package, Internal Reference, 1LSB INL (12 Bits)
12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V, 2-Channel Differential, 14mW, MSOP Package
LTC2360/LTC2361/LTC2362 12-Bit, 100/250/500ksps Serial ADC in TSOT 16-Bit, Serial SoftSpanTM IOUT DAC 12-/10-/8-Bit Single VOUT DACs
LTC1666/LTC1667/LTC1668 12-/14-/16-Bit, 50Msps DACs
SoftSpan is a trademark of Linear Technology Corporation.
24 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2008

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